1. Field of the Invention
The present invention relates to circuits for testing integrated circuits and, more specifically, to a circuit provided on the same chip as the integrated circuit for testing functional blocks included in the integrated circuit.
2. Description of the Prior Art
FIG. 1 is a schematic diagram of a LSI constituted by a composite functional block comprising a RAM 10, a control circuit 15 and an arithmetic unit 16. A scan path (data path) is employed to facilitate testing in this LSI. The scan path 17 is provided between an input terminal X0 and an output terminal Y0 and used for testing the RAM 10. The scan path 18 is provided between an input terminal Xl and an output terminal Y1 and used for testing the control circuit 15 and the arithmetic unit 16 as well as the RAM 10.
FIG. 2 shows details of the portion 19 in FIG. 1. FIG. 2 shows a memory cell array 6 of 4 bit.times.M words structure as an example. On the scan path 17 successively arranged are scan latch 1a comprising multistages of latches for holding row address signals; a scan latch 1b comprising two stages of latches for holding a CE (chip enable) signal and a WE (write enable) signal; a scan latch 28 comprising four stages of latches 1f for holding 4 bit test data; and a scan latch 29 constituted by four stages of latches 1f for holding 4 bit output data from the memory cell array 6. The address buffer 2 receives row address signals written in the scan latch 1a. The row decoder 3 receives outputs from the address buffer 2. The outputs from the row decoder 3 are inputted to the memory cell array 6.
The control circuit 5 receives signals written in the scan latch 1b. The outputs of the control circuit 5 are inputted in the address buffer 2, the column decoder 4 and in a Din buffer (data input buffer) 8. The Din buffer 8 receives outputs from the scan latch 28. A Do buffer (data output buffer) 9 receives read outputs from the memory cell array 6 through a multiplexer 7. The outputs from the Do buffer 9 are written in the scan latch 29 in bit by bit correspondence. The multiplexer 7 selects one of a plurality of columns in the memory cell array 6 based on the signal from the column decoder 4 to input test data from the Din buffer 8 to the memory cell array 6 and receives output from the memory cell array 6 to transmit the same to the Do buffer 9. A strobe 14 is to extract outputs from the Do buffer 9 at a constant timing.
The operation will be described in the following. First, test data, a CE signal, a WE signal and a row address signal are successively inputted in this order to the scan path 17 from the terminal X0. Now, each of the scan latches 1a, 1b, 28 and 29 is constituted by latches interposed in series in association with the scan path 17, so that every time a signal or the test data is inputted, the signal or the data which is already being inputted in any one stage of latch in each of the scan latches 1a, 1b, 28 and 29 is shifted to the latch in the succeeding stage, and a new signal or data is written in the latch of preceding stage. When the row address signal, CE signal, WE signal and 4 bit (the number of bits of the memory cell array 6 to be tested) test data are inputted, the writing is completed.
The row address signal written in the scan latch 1a is supplied to the row decoder 3 through the address buffer 2. Therefore, the row decoder 3 selects one row out of the rows in the memory cell array 6. The CE signal and the WE signal written in the scan latch 1b are applied to the control circuit 5. The control circuit 5 controls the driving of the address buffer 2, the column decoder 4, Din buffer 8 and the Do buffer 9. After the selection of the memory cell array 6 is carried out in this manner, the 4 bit test data written in the scan latch 28 are read out to be written in the memory cell at the selected position in the memory cell array 6 through the Din buffer 8. The 4 bit test data written in the memory cell array 6 are read through the multiplexer 7 and the Do buffer, and written in the scan latch 29 in bit by bit correspondence. The test data written in the scan latches 28 and 29 in this manner are read one by one from the output terminal Y0. The collation of the data read from the scan latches 28 and 29 is carried out in another circuit, not shown. Meanwhile, the output data from the Do buffer 9 is sampled at a designated timing by using the strobe 14.
As described above, in a conventional circuit a plurality of scan latches are arranged in series, with the data inputted and outputted one by one successively to and from each of the latches. Therefore, the input and output of the row address signal, CE signal, WE signal and test data whose number is equal to the bit number of the integrated circuit to be tested should be carried out to complete the test of one word. Consequently, there is a disadvantage that a long time is required for inputting and outputting signals and test data. In addition, the input and output of the test data and the collation thereof should be done by separate circuits in the conventional circuit, with the time for collation further elongating the time for testing.